Conversion of a digital number into a clock signal having a frequency that has a mathematical relationship to (e.g., proportional) the digital number is a widely used technique in modern electronics. One circuit that can make use of this conversion is a phase-locked loop (PLL). In an example, a digital PLL can convert the digital number that represents clock frequency into a voltage or current using a digital-to-analog converter (D2A) and then uses the resulting analog voltage or current to control an analog voltage or current controlled oscillator.
FIG. 1 illustrates another technique known as direct digital synthesis (DDS) 100. DDS uses a digital accumulator 102 which is clocked by a fixed clock 104 (usually quartz oscillator derived). This fixed clock 104 (also referred to herein as a “master clock”) is used to create an output clock signal 106 (also referred to herein as a “synthesized clock”) at the desired frequency. A DDS 100 accepts a number (also referred to herein as a frequency control word (n)) into the accumulator 102 which represents a phase step that is applied every master clock cycle. Once the accumulator 102 is full, overflow occurs and the most significant carry out is discarded. This condition corresponds to the phase output of the accumulator having traversed fully 360 degrees and with the overflow, returning to a small phase value. This process is continually repeated. The required number of most-significant sums from this accumulator 102 can be tapped to provide whatever phase resolution is required. Instantaneous phase may then be converted to instantaneous amplitude using a sin or cosine read-only-memory (ROM) look up table 108. This digital amplitude data may then be converted to an analog quantity using a D2A 110. After the D2A 110, using analog filters 112, the signal may be filtered to produce a final sin or cosine waveform.